8/31/2023 0 Comments Mesi cache coherence![]() Also back to the main memory from one of the other processor that has a modified state is removed in using a proposed protocol when it is invalidated as a result of writing to that location that has the same address because in all cases it depends on the latest value written and if back to memory is used to protect data from loss preprocessing steps to IES protocol is used to maintain and saving data in main memory when it evict from the cache. We have proposed in this research integrating two states of MESI's cache coherence protocol which are Exclusive and Modified, which responds to a request from reading and writing at the same time and that are exclusive to these requests. are the famous protocols to solve cache coherency problem. So, cache coherency protocol is very important in such kinds of system. In such systems, when installing different caches in different processors in shared memory architecture, the difficulties appear when there is a need to maintain consistency between the cache memories of different processors. To improve the efficiency of a processor in recent multiprocessor systems to deal with data, cache memories are used to access data instead of main memory which reduces the latency of delay time. Test results were taken by using test bench, and showed all the states of the protocol are working correctly. The protocol used in this design is the modified, exclusive, shared and invalid (MESI) protocol. In this paper a special circuit is designed using very high speed integrated circuit hardware description language (VHDL) coding and implemented using ISE Xilinx software. So if one core requestes a block of data from main memory to its cache, there should be a protocol to declare the situation of this block in the main memory and other cores.This is called the cache coherency or cache consistency of multi-core. All cores are similar in their design, and each core has its own cache memory, while all cores shares the same main memory. This new design makes the processors to work simultanously for more than one job or all the cores working in parallel for the same job. ![]() The new chips of processors called a multi-core processor. The idea is to have a common bus connecting the private caches and the shared next level cache or main memory. In modern techniques of building processors, manufactures using more than one processor in the integrated circuit (chip) and each processor called a core. The general approach to implement cache coherence is the SNOOPY based methods.
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